Modelling of Noise in PLL’s Using sample essay
Hardware description languages (HDLs) exist to describe hardware. In this they differ from traditional programming languages, which generally exist to describe algorithms. To properly describe hardware, one must be able to describe both the behaviour of the individual components as well as how they are interconnected. Hardware description languages have two primary applications: simulation and synthesis. With simulation, one applies various stimuli to an executable model that is described using the HDL in order to predict how it will respond. Simulation allows you to understand how complex systems behave before you incur the time and expense of implementing them. Synthesis is the process of actually implementing the hardware. Here the assumption is that the HDL is used to describe the hardware at an abstract level using component models that do not yet have a physical implementation, and that synthesis is the act of creating a new refined description with equivalent behaviour at the inputs and outputs that uses components that do have a physical implementation.
The goal for HDLs used for simulation is expressiveness: they should be able to describe a wide variety of behaviours easily. The goal for HDLs used for synthesis is realizability: they should only allow those behaviours that can be converted into an implementation to be described. As such, if a single language is used for both simulation and synthesis, then generally synthesis only supports a relatively constrained subset of the language. Currently only digital finite-state machines are automatically synthesized. In this case, the desired behavior is described at the register-transfer level (RTL) using a well-defined subset of an HDL. Synthesis then converts the RTL description to an optimized gate-level description. Implementations of the gates are available from a library of standard cells.
Automated synthesis of analog or mixed-signal systems from a description of its desired behavior has not progressed to the point where it is practical except in a few very restricted cases. Further more, it is not clear that it will ever reach this point. Focus is on manual synthesis, the process undertaken by designers to convert high-level design requirements to an implementation that meets those requirements. This process, also known as the design process, is not one that traditionally uses hardware description languages when it involves the design of analog or mixed-signal systems. However, as mixed-signal systems become more complex there comes a time where it becomes impractical to design them without using abstraction. It is this point where use of HDLs becomes necessary as they are used to express the abstraction.
There are currently two HDLs available for describing mixed-signal hardware: Verilog-AMS and VHDL-AMS. As the names imply, they are extensions to the traditional Verilog and VHDL digital HDLs that are intended to support modelling of analog and mixed-signal systems. Though these languages have different strengths and weaknesses, they are intended to be used on the same types of circuits, in the same ways, to produce the same results. As such, they are competitors. To a large degree, the choice between them is currently determined by what language is being used for the digital part of the system.
The Verilog Family of Languages
Verilog-AMS is a modeling language for mixed-signal systems. It is primarily designed to upport simulation of mixed-signal systems by allowing the system to be described to the simulator. However, mixed-signal systems represents a very broad class of systems and must support a wide variety of situations. As such, Verilog-AMS is a language that has a diverse range of capabilities. The term “mixed-signal” suggests systems made up of parts that process digital signals and parts that process analog signals. As such, Verilog-AMS is a language that supports the description of both digital and analog components. Verilog-AMS is the merger and extension of two languages, Verilog-HDL and Verilog-A. These three languages currently make up the Verilog family of languages. Verilog-HDL allows the description of digital components and Verilog-A allows the description of analog. Verilog-AMS combines these two languages and adds additional capability to allow the description of mixed-signal components.
The term Verilog-AMS is used when referring to just the full AMS extensions and Verilog-A/MS when referring to both Verilog-A and Verilog-AMS. Digital signals are discrete-event signals with discrete values. In other words, they are signals that are constant for a period of time, and then abruptly change to a new value. With digital signals there are generally only a small number of possible signal values, typically two, designated true and false, high and low, or zero and one. The Verilog-HDL language was designed to handle such signals, and the systems that generate them. Analog signals are signals that vary continuously, meaning that the value of the signal at any point may be any value from within a continuous range of values.
There are two ways in which this typically occurs, as shown in Figure 1. Either the signal is piecewise constant versus time, meaning that it holds its value for a period of time before jumping to a new value, or it is continuous versus time, meaning that its value varies smoothly as a function of time. The former signals are referred to as being analog discrete-event signals and the latter are continuous-time signals. The figure shows the analog discrete-event signal jumping between values at regular intervals, but this is not necessary. Both the value, and the time at which the jump-events occur can be irregular.
Verilog-A is designed to allow modeling of systems that process continuous-time signals. While it can also handle systems that process the other types of signals, it is not efficient for doing so. Verilog-A has been around for many years, though not nearly as many as Verilog-HDL. Since Verilog-AMS combines Verilog-HDL and Verilog-A, as shown below, [pic]
It inherits the ability to handle systems that process both digital and continuous-time analog signals. It also adds the ability to efficiently support systems that process analog discrete-event signals. Verilog-AMS is expected to have a big impact on the design of mixed-signal systems because it provides a single language and a single simulator that is shared between analog and digital designers, and between block designers and system designers. It will be much easier to provide a single design flow that naturally supports analog, digital and mixed-signal blocks, making it simpler for these designers to work together. Verilog-AMS makes it substantially more straight-forward to write behavioral models for mixed-signal blocks, and brings strong event-driven capabilities to analog simulation, allowing analog event-driven models to be written that perform with the speed and capacity inherited from the digital engines. This is very important, because most of the analog and mixed-signal models used in high-level simulations are naturally written using event-driven constructs. For example, blocks like ADCs, DACs, PLLs, converters, discrete-time filters (switched-capacitor), etc. are easily and very efficiently modeled using the analog event-driven features of the AMS languages.
Mixed-signal simulators, by their very nature, combine two different methods of simulation: event-driven simulation as found in logic simulators, and continuous-time simulation as found in circuit simulators. As such, they are said to have two kernels; a discrete-event kernel and a continuous-time kernel. These two kernels are an essential feature of any mixed-signal simulator. Indeed, it is what separates mixed-signal simulation from other types of simulation.
There are five main reasons why engineers use Verilog-AMS:
1. to model components,
2. to create test benches,
3. to accelerate simulation,
4. to verify mixed-signal systems, and
5. to support the top-down design process.
A phase-locked loop (PLL) is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator. A phase-locked loop or phase lock loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a “reference” signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. A phase-locked loop is an example of a control system using negative feedback. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors.
The phase frequency detector (PFD) detects the difference in phase and frequency between the reference clock and feedback clock inputs and generates an “up” or “down” control signal based on whether the feedback frequency is lagging or leading the reference frequency. These “up” or “down” control signals determine whether the VCO needs to operate at a higher or lower requency, respectively. The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter. The loop filter converts these signals to a control voltage that is used to bias the VCO. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increases.
A down signal decreases the VCO frequency. The VCO stabilizes once the reference clock and the feedback clock have the same phase and frequency. The loop filter filters out jitter by removing glitches from the charge pump and preventing voltage over-shoot. One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset (also called the steady-state phase error). The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible.
Phase noise is another type of jitter observed in PLLs, and is mostly caused by the amplifier elements used in the circuit. Some technologies are known to perform better than others in this regard. The best digital PLLs are constructed with emitter-coupled logic (ECL) elements, at the expense of high power consumption. To keep phase noise low in PLL circuits, it is best to avoid saturating logic families such as transistor-transistor logic (TTL) or CMOS. Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called supply and substrate noise rejection. The higher the noise rejection, the better.
Our project aims in modelling the noise of PLL through Verilog AMS. Platform : Smash 5.13.0
Smash is all in one mixed signal, multi level, multi-language, multi-domain-simulator. All in one means SMASH support the major description languages, be they analog or logic, within a single simulation kernel (SPICE, Verilog-HDL, Verilog-AMS, VHDL, VHDL-AMS, ABCD, and C/C++). Mixed-signal means that SMASH handles both analog and continuous signal and discrete logic signals. Multi-level means that SMASH provides circuit description at all levels: electrical, structural, functional, and behavioural levels.
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